Semiconductor-Grade Ceramics Enable Future Electronics
Engineered ceramics enable clean, consistent wafer processing, front-end semiconductor fabrication, and back-end chip packaging.
Perhaps the most impactful invention in modern history, the transistor is at the core of semiconductor devices and has dramatically transformed virtually every industry while helping spawn many new ones. As illustrated in Figure 1, today’s microchips can contain over a billion transistors and are improving our cars, phones, and refrigerators—empowering internet searches, genetic research, and smart sensors. How different would our world be today without these integrated circuit (IC) “microchips?”
As is often the case, engineered ceramics are behind the scenes—enabling the impressive semiconductor fabrication process by delivering consistent performance despite stringent thermal, chemical, electrical, mechanical, dimensional, and cleanliness requirements. These complex integrated circuits are built one layer at a time on semiconducting wafers (typically silicon), in some of the most aggressive and challenging environments. Sophisticated semiconductor processing equipment is designed to deposit, pattern, etch, and anneal numerous layers of tailored dielectric and metal materials using highly reactive gasses, corrosive liquids, powerful plasma, and dramatic temperature changes. Advanced ceramics are among the only materials that can be engineered to endure hundreds of aggressive cycles in these harsh environments while delivering clean, consistent performance.
Equally amazing is the pace at which semiconductor processing technology has advanced. In 1965, Gordon Moore, co-founder of Fairchild Semiconductor and Intel, observed the trend that computing power was doubling approximately every two years and predicted that this astounding rate of innovation would continue for at least another 10 years. More than five decades later, “Moore’s Law” has held true as the semiconductor industry continues to find new ways to sustain this exponential rate of advancement.
Semiconductor technology is often defined by “node” size, the physical size of the transistor. The smaller each transistor becomes, the more transistors fit on a chip, the faster they switch, the less energy they consume, and the cooler the chip runs. From a 10 µm technology node in 1971, semiconductor companies have continued to develop new technology nodes that enable faster, cheaper, smaller chips—achieving a 700x reduction to the current 14 nm node.
More transistors means more processing power. Compared to those first microprocessors, today’s chipsets deliver 3,500 times the performance at 90,000 times the energy efficiency and at 1/60,000th the cost. How many industries can boast continuous improvement like that? If automobiles had progressed at the same rate, cars today could travel at almost 300,000 mph, get over 2,000,000 mpg and cost only $0.04.1
From Lab to Fab
It is one thing to predict the theoretical potential of ICs, but achieving these performance gains year after year in mass production is nothing short of amazing. Semiconductor fabrication plants (fabs) use several advanced processes to manufacture these complex, microscopic circuits. Fabs are categorized by the diameter of substrates or “wafers” they are tooled to produce. Over the past decades, semiconductor wafers and the processing equipment used to build ICs on them have gradually grown from 1 in. (25 mm) to 12 in. (300 mm) diameter—a 144-fold increase in area (see Figure 2). By expanding both the surface area and number of vertical layers, fabs are able to increase IC computing power while making more chips at a time.
Beginning as molten silicon, a semiconductor wafer experiences dozens to hundreds of individual process steps on its way to becoming a batch of ICs a few weeks later (see Figure 3):
- Wafer processing
- Front-end fabrication
- Back-end packaging
Semiconductor equipment manufacturers are increasingly taking advantage of the unique properties of ceramics in each of these stages—leveraging mechanical, chemical, thermal, and electrical performance to handle wafers for better yields, to accelerate processing for higher throughput, and to extend the useful life of equipment for lower operating costs. Taking a closer look at some examples will demonstrate how engineered ceramics enable a variety of semiconductor processes.
Clean and Flat
With IC features measured in nanometers (nm), or billionths of a meter, a single dust particle in a critical area can kill a whole chip. As such, semiconductor fabs go to extreme measures to maintain the purity and cleanliness of the process, including: employees fitted with “bunny suits,” material layers deposited from high-purity gasses, and robotic equipment to reduce particle generation from handling. The air inside a Class 1 cleanroom has a maximum of one particle 0.5 µm or larger—more than 10,000 times cleaner than an operating room, or about 1,000,000 times cleaner than the air we normally breathe. Anything exposed to the wafer needs to be pristine, clean and resistant to particle generation.
The silicon wafers used as semiconductor substrates are sliced from large ingots of electronic-grade silicon (EGS), which are typically 300 mm in diameter and 2 m high. Each ingot is formed as a single crystal by slowly rotating and pulling 1,400°C molten silicon contained in pure, thermally stable, fused quartz crucibles up to 800 mm (32 in.) in diameter.
Flat, smooth, and uniform wafers are critical to high yields and low defect densities, especially as node sizes get smaller and the number of layers increases. Chemical mechanical planarization (CMP) combines an acidic or basic solution with abrasive polishing media to deliver smooth planar surfaces on the original wafer substrate and for the subsequent deposition of multiple layers of materials and interconnects. Silicon carbide polishing tables combine high chemical and abrasion resistance with extreme stiffness to enable pristine flat, polished surfaces.
Silicon wafer processing uses both conventional furnaces and specialized rapid thermal processing equipment for high-temperature (700-1,200°C) procedures, including diffusion, oxidation, deposition, and annealing. Many thermal processes use vertical or horizontal furnaces to improve throughput by processing wafers in large batches.
Vertical wafer boats with pedestals or horizontal wafer boats with paddles are engineered to hold the wafers in precise position through these high temperatures, sometimes for long durations. With considerations such as a large number of wafers and their associated weight, tight dimensional tolerances, and high temperatures, silicon carbide (SiC) ceramic components are increasingly replacing quartz components due to their higher thermal stability, clean particle-free surface, and superior barrier to mobile ions.
Several deposition processes, including chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), and atomic layer deposition (ALD), rely on precise temperature control and uniformity across the wafer surface. Engineered heaters deliver consistent temperature across wafer surfaces, often including multiple heating zones, for thermal uniformity control up to 750°C. Aluminum nitride (AlN) is the preferred material for pedestal heaters, combining high thermal conductivity, strong electrical resistivity, and a coefficient of thermal expansion similar to silicon.
Rapid thermal processing (RTP) systems provide fast, consistent, single-wafer processing. These systems are capable of ramping temperature at rates up to 200°C per second, compared to the 5-10°C per minute rate in a conventional furnace. The additional thermal control RTP provides is useful in applications such as rapid thermal annealing (RTA), rapid thermal chemical vapor deposition (RTCVD), and rapid thermal oxidation (RTO).
Since RTP processes are among the most demanding applications, CVD silicon carbide (CVD SiC) is an optimal material due to its combination of high thermal shock resistance, low thermal mass, high strength and stiffness, and ultra-pure composition. In addition, the electrical resistivity and optical/infrared transmissivity of CVD SiC can be tuned for application-specific requirements. CVD SiC components provide superior durability and are exceptionally resistant to high-temperature, in-situ etching in acidic environments, like the gaseous HCl and concentrated HF/HNO3 used for wet cleaning.
Although ceramic components can be utilized in both wet (chemical) etch and dry (plasma) etch processes, almost all advanced semiconductor fabs use a plasma etch based on the nanometer-scale patterned features required. Etch chamber components such as lids and rings are engineered to resist erosion from the harsh plasma etch environment, transmit microwave energy, reduce particle shedding, and endure the aggressive cleaning required. Semiconductor-grade aluminas (Al2O3), yttria (Y2O3), and yttria coatings are an excellent fit based on their plasma etch resistance, controlled dielectric properties, and high purity.
In photolithography and wafer inspection, precise dimensional tolerances and surface flatness are critical for accurate and stable positioning in stepper chucks, tables, and wafer stage components. SiC components provide an excellent combination of high stiffness, ability to hold ultra-flat and smooth surfaces, extreme wear resistance, light weight, and low thermal expansion. For clean wafer handling, low-surface-contact features help minimize the risk of back-side particles.
After a semiconductor wafer completes the front-end processing, it is diced and prepared for back-end packaging. Wire bonding is used to make interconnections between the IC and its packaging. The latest wire bonding technology is transitioning from gold connections to copper, providing significant cost savings. Since copper is a much harder material than gold, traditional tooling is ineffective at making quality copper bonds and erodes quickly.
Ceramic capillaries are specifically engineered to deal with this issue and are being used to deliver consistent, high-reliability bonds, as well as superior lifetime. Capillary tips are textured to micron-scale finishes to provide optimal performance for specific wire types.
Future Semiconductor Trends
From an advanced ceramics perspective, the cycle of innovation will continue:
- Semiconductor equipment engineers work to increase throughput and yield using faster, more aggressive processes
- These more aggressive processing conditions challenge the in-situ performance and lifetime of existing components (e.g., more rapid thermal treatment, more aggressive chemical solutions, and more powerful plasma)
- Ceramic materials improvements increase performance and lifetime under these new, more challenging conditions
Some of the semiconductor development trends further challenge material and component performance, driven by the combination of:
- Transition from 14 nm to 10 nm technology nodes (and beyond)
- Shift from 300-mm (12-in.) wafers to 450-mm (18-in.) wafers
- Increasingly complex chip architecture—3D designs with multiple patterning, interconnects, gates, and junctions
- Atomic layer engineering and processing
- More aggressive chemistries and thermal processing
- Requirement for increased uniformity, cleanliness and precision
Although we cannot predict or imagine all of the semiconductor innovations coming, two things are certain. Semiconductor companies will continue to advance processing technology to make chips faster, cheaper and more powerful. Consequently, ceramic components will grow in importance and be pushed to deliver even better performance to support this challenging and exciting industry.
1. Intel, Inc., “50 Years of Moore’s Law,” video retrieved from http://www.intel.com/content/www/us/en/silicon-innovations/moores-law-technology.html.