Advanced Ceramics

Shaping the Future

March 1, 2008
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The shallow trench isolation (STI) process is a key step in the production of leading-edge integrated circuit devices. In this process, silicon dioxide-filled trenches serve to electrically isolate different active regions in the circuit where transistors will be fabricated. For large-scale, wafer-level fabrication of nanodevices, the surface of a silicon wafer must be perfectly flat and defect-free.

Traditionally, fumed silica or colloidal silica slurries have been used for the chemical mechanical planarization (CMP) of STI features. Device manufacturers have extended the use of silica-based slurries for STI CMP down to the 90 nm technology node, where they are still effective in removing bulk oxide topography. However, they lack the ability to stop on the silicon nitride layer, which is an important requisite of the slurry. For 65 nm technology and below, ceria-based slurries, with high oxide-to-nitride selectivity, are replacing silica slurries in order to achieve the more rigorous performance targets.

Many methods can be used to make ceria particles, including solid-state calcination/milling and novel approaches such as growth in solution, flame pyrolysis, microwave-assisted hydrothermal, hydrothermal crystallization, micro-emulsion, sol-gel methods, and solvothermal synthesis. This article compares CMP defectivity performance that has been obtained with three of these methods. Collectively, these technologies offer the best opportunities for ongoing improvements that will be required to meet the semiconductor industry’s demand for reductions in circuit size at each technology node.

Published work explores the shapes and touts the potential advantages of some of these novel particle manufacturing techniques.1,2 More detailed defect studies were recently performed with ceria particles made through optimized solid-state, hydrothermal and flame pyrolysis routes. In contrast to the initial work,2 this study used added defect detection capabilities, including highlighting defects with a wet etch process, classifying defects with SEM, and added optical defect recipe refinement. The defect performance of CMP slurries made with optimized solid-state ceria particles far exceeds that of optimized solution-grown or flame-synthesized ceria particles.

Figure 1. TEM photo of optimized solid-state ceria particle (magnification is about 100,000 x, bar = ~ 10 nm).

Solid-State Ceria Particles

The most common ceria process starts with a raw form of cerium (cerium hydrate, nitrate, carbonate, etc.) and converts it to cerium oxide through a solid-state calcination process at > 600ºC, followed by particle size reduction through a milling process. Using these techniques, several critical output parameters of the ceria particles need to be measured, including crystallite characteristics, surface area, porosity and particle size distribution (including oversized particles). These key parameters need to be tightly controlled, and proprietary processes developed to enable the manufacture of consistent, low-defect particles using these techniques.

In 2004, a ceria-based, single-component, high-selectivity STI CMP slurry was developed that allowed device manufacturers to move from 90 to 65 nm technologies. There have been multiple improvements over the last several years to drive the particle performance to the level necessary for use at the 45 nm technology node, with continuous improvement of this process for future technology nodes.

Patented second-generation, high-selectivity slurries utilizing an optimized low-defectivity ceria particle are performing successfully in high-volume manufacturing of 65 nm Flash devices and 45 nm node STI logic devices (see Figure 1). The new commercial STI slurry was used in these comparison studies.

Figure 2. TEM photo of solution-grown ceria particle (magnification is about 500,000 x, bar = ~ 10 nm).

Solution-Grown Ceria

Using the proper hydrothermal synthesis conditions, including dopants, ceria particles with various shapes and sizes can be created. Joint research with the Georgia Institute of Technology determined that the shape of CeO2 particles in the size range of 3-10 nm was dominated by a truncated octahedral with flat surfaces that agglomerated to form a lattice-matched coherent interface. The faceted shape also resulted in a textured distribution of nanoparticles deposited onto a substrate surface, with a preferred orientation of [110]. These structural characteristics were thought likely to affect their performance in technological applications.1

For these more recent studies, the solution-grown particles were synthesized using a hydrothermal process wherin a cerium precursor was heated at > 250ºC in a closed system under high pressure. Particle properties like primary and secondary particle size were tuned to achieve good polishing rates on silicon dioxide, a primary gate to conduct an effective defect study for STI CMP.

During an extensive research and development effort, the type and level of dopants and the hydrothermal process were tuned to control the particle properties to get good rates and to minimize defectivity. The rounded particles shown in Figure 2 are the result of this extensive optimization and are typical of the particles used in these polishing defect studies.

Figure 3. TEM photo of flame-synthesized ceria particles (magnification is about 200,000 x).

Ceria from Flame Pyrolysis

In the flame spray pyrolysis method of creating ceria particles, cerium precursors are injected into a flame via an atomizer, and the ceria particles are grown in a combustion chamber. A myriad of shapes and sizes (including spherical) of ceria particles can result with the use of dopants when the flame system is tuned properly.

Collaborative research with the Georgia Institute of Technology; Cranfield University; Peking University; the National Center for Nanoscience and Technology in Beijing, China; and Nanocerox, Inc. developed an approach for large-scale synthesis to convert ceria polyhedral nanoparticles into single-crystal ceria nanospheres without faceting by doping with titanium. The particles were completely encapsulated by titanium, with data showing that the surface amorphous layer is TiO2. Performance tests of slurries formulated with these spherical ceria nanoparticles demonstrated an 80% reduction in polishing defects and a 50% increase in the silica removal rate compared to traditional ceria-based slurries.2

The type and level of dopants, as well as the flame process, were optimized for both polishing rates and defectivity in a manner similar to the hydrothermal system. The ceria particles with spherical morphology shown in Figure 3 are the result of this optimization and were used for the defect testing in these studies.

Figure 4. Scratch defect comparison of CMP slurries shows that the one using optimized solid-state ceria particles provides superior performance compared to those using flame-synthesized or solution-grown ceria particles.

Defectivity Results

The defectivity results of the different ceria particles were generated as follows. 200 mm patterned STI dynamic random access memory (DRAM) wafers were purchased from Adcon Labs and polished on an Applied Materials 200 mm Mirra platform using Rohm and Haas IC1000 polishing pads with a Suba IV backing. The wafers were targeted to have all silicon dioxide removed above the silicon nitride structures.

Post-CMP cleaning was carried out using an Ontrak double-sided brush scrubber with SC1 cleaning chemistry. The defects were highlighted with hydrofluoric acid, and the silicon nitride layer was stripped with hot phosphoric acid on a linear automated chemical transfer etch station from JST Corp. Optical defect inspection was carried out using an Applied Materials WF-736 Orbot tool, and defects were classified using an Applied Materials SEM-vision CX Plus.

The post-etch defectivity results can be seen in Figure 4, which illustrates far superior scratch performance when using the optimized solid-state ceria particles vs. both the optimized flame-synthesized ceria and optimized solution-grown ceria. These results disprove a perception in the semiconductor industry that round particles deliver superior performance. Indeed, the collaborative team working on the flame-synthesized spherical ceria particles expected improved defectivity performance because of the widely-held belief that the relatively sharp edges of the cubic-shaped ceria particles may gouge and/or scratch wafer surfaces that are being planarized.

The lack of such sharp edges and corners and the ability to roll freely on the wafer surface during polishing was thought to substantially reduce the adders and scratches.2 Cabot also presented work showing that “round-cornered” ceria particles were better than “common” ceria particles when substituted into some of their slurries, thus reducing defectivity by 70%.3

However, the bias toward round particles has few empirical references to support it and mounting data that refute it. A recent performance study by Umicore Research and IMEC showed that slurries formulated with rounded ceria particles had lower removal rates and higher levels of defectivity.4

Other Contributing Factors

Many references suggest that the dominant mechanism for material removal may not be the mechanical plowing of the slurry particles into the wafer surface.5 The calculated indentation depth of a slurry particle into the surface is often on an atomic or sub-atomic scale; it is unlikely that surface materials are “plowed” away in molecular or atomic dimensions.

Rather, surface chemistry plays an important role. Ceria reacts with the silica surface to remove it. The surface chemistry of the optimized solid-state ceria particle forms stronger bonds to silica, and mechanical action cleaves the weaker silica bonds to achieve planarization. It is known that larger particles at the top end of the particle size distribution generate defects during polishing, so control of these large particle counts is critical for any particle morphology.

Conclusions

Improved ceria-based STI slurries will be needed for the coming technology nodes, with reductions in defect rates of at least 50% required for each new technology advance to be commercially viable. Many parameters can make a good ceria particle, and particle morphology is just one such parameter.

Results thus far have shown the most consistent and high-quality performance from optimized solid-state synthesis, which has been confirmed on process wafers by customers. The solid-state technology is robust and has achieved a level of process control that allows high-volume manufacturing of high-selectivity, low-defectivity ceria particles. These particles are performing successfully in CMP slurries supplied for 45 nm node devices, and offer the greatest immediate opportunity for further optimization to meet ever-escalating challenges.

For more information, contact Ferro Electronic Material Systems at 1789 Transelco Dr., Penn Yan, NY 14527; (315) 227-5345; fax (315) 536-0376; e-mail merricksd@ferro.com; or visit www.ferro.com.

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